This invention relates to programmable logic, and in particular to an active driver circuit particularly suited for a high speed programmable logic device.
A programmable logic device (PLD) is a programmable integrated circuit that allows the user of the circuit, using software control, to customize the logic functions the circuit will perform. A typical PLD consists of an array of identical logic cells that can be individually programmed, and which can be arbitrarily interconnected to each other to provide internal input and output signals, thus permitting the performance of highly complex combinational and sequential logic functions. The program is implemented in the PLD by setting the states of programmable elements such as memory cells.
One type of PLD, known as programmable logic arrays (PLA), is a combinatorial two-level AND/OR integrated circuit, which can be programmed to perform sum-of-products logic. Such devices typically consist of a series of AND gates having input terminals which can be programmably connected to chip input signals, and a series of OR gates which may be programmably connected to receive the output signals from the AND gates.
Another type of PLD is known as programmable array logic (PAL). PALs use a fixed OR array and bidirectional input/output pins. A disadvantage of both PALs and PLAs is the lack of density with which they may be progranmed. In other words, although the array is capable of performing many logic functions, utilization of the array is not as complete as desirable. Furthermore the size of the array increases faster than its programming capability.
A response to this problem has led to the development of the field programmable gate arrays (FPGAs) which have "macrocells" or logic cells in programmable logic devices. A macrocell or logic cell is a small grouping of logic capable of performing many different functions, and being selectively interconnectable to other macrocells or logic cells. This allows the logic in the programmable logic device to assume a more granular structure in which pieces of the logic communicate with other pieces, to provide an overall more efficient utilization of the integrated circuit. For purposes of the present specification, "programmable logic device" is defined as a programmable array logic (PALs), programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), and other types of programmable logic devices (PLDs).
Many PLDs may be programmed only once. This may be performed as a final process during fabrication of the device. Another type of PLD may be programmed subsequent to formation. This is typically achieved by connecting the AND and OR arrays, as well as to and from the macrocells, by various fusible connections.
Other types of PLDs may be programmed multiple times, i.e., they may be reprogrammed. To that end, the PLDs typically include erasable programmable read only memory (EPROM) cells, electrically erasable read only memory (EEPROM) cells or the like to retain the programming information, typically referred to as configuration data. Reprogramming is achieved by changing the configuration data contained in the memory cells.
Reprogrammable PLDs also employ random access memory (RAM) cells to store configuration data. Typically static random access memory (SRAM) cells are employed to store the configuration data. Unlike EPROM and EEPROM cells, configuration data stored in SRAM cells is lost when power to the PLD is terminated. However, SRAM cells are easily programmable and require less power to operate than the EPROM and EEPROM cells, making SRAM an attractive element in which to store configuration data for a PLD. To that end, there are many prior art attempts employing SRAM in a PLD.
U.S. Pat. No. 5,128,559 to Steele discloses a PLD having a macrocell that employs RAM, to perform logic functions, and circuitry which allows writing of data to the RAM during use. Each macrocell may be configured at programming time to function as a standard RAM or to perform logic functions.
U.S. Pat. No. 5,809,281 to Steele et al. discloses a PLD having a number of configurable function blocks, each of which is separately configurable to function as either programmable logic or a block of SRAM. Each configurable function block may include a volatile logic array comprised of an array of "AND" gates and an array of "OR" gates with programmable connections. The programmable connections in the volatile logic array comprise SRAM cells. These SRAM cells are capable of functioning in one of two states. In a first state, the SRAM cells provide programmable connections, which direct the logic operations in the volatile logic array. In the second state, the SRAM functions as a block of SRAM using standard read/write modes. As described above, the prior art provides PLDs that have macrocells with one of two discrete functions.
What is needed, however, is a PLD that provides more flexibility in the macrocell by allowing the same to concurrently provide multiple functions.